1. Field of the Invention
The present invention relates to a semiconductor device, more particularly a semiconductor-on-insulator device including a field-effect transistor, and to its fabrication method.
2. Description of the Related Art
Energy conservation and power efficiency are demanded in modern electrical and electronic devices, including consumer devices, automotive devices, and lighting devices. Light emitting diode (LED) illumination, photovoltaic power generation, and power management, in which power is supplied to only the necessary operational blocks in an electrical or electronic device, are among the technologies being developed to meet these demands. There are also demands for greater power efficiency and smaller size in the field of power electronics, particularly regarding the metal-oxide-semiconductor field-effect transistors (MOSFETs) that consume large amounts of power in power electronics circuits. A recent trend is the development of integrated circuits that include a power device, its control circuit or driving circuit, and other peripheral circuitry on a single chip. Compared with bulk silicon substrates, semiconductor-on-insulator (SOI) substrates are advantageous because they can provide almost complete electrical isolation between circuit elements with different functions. This makes the SOI device structure particularly suited for single chips including both power devices, to which high voltages are applied, and their peripheral circuits.
A field-effect transistor (FET) with an SOI device structure is known to be particularly vulnerable to floating body effects, also referred to as floating kink effects or floating substrate effects. In an SOI substrate, the semiconductor layer overlies a buried insulating layer, which separates the semiconductor layer from the underlying substrate layer or base layer. An FET fabricated on an SOI substrate has a body region surrounded by a source region, a drain diffusion region, and the buried insulating layer. When a conductive channel is formed in the body region between the source and drain diffusion regions and impact ionization occurs around the edge of the body region next to the drain diffusion region, electron-hole pairs are generated. Majority carriers (holes in an n-channel FET, electrons in a p-channel FET) with no place to go may then accumulate in the body region, altering the potential of the body region (referred to below as the body potential). Such alteration of the body potential (floating of the body potential) can alter the threshold voltage of the FET or cause parasitic bipolar operation; these effects are what are referred to as floating body effects.
In Japanese Patent Application Publication (JP) 2005-276912, Hara discloses an SOI MOSFET with a multi-RESURF structure in which the semiconductor layer includes source-body connection regions through which carriers generated by impact ionization can escape. In JP 2000-269509, Hirano discloses an SOI MOS transistor having a body potential extraction region that provides a similar escape path for carriers generated by impact ionization.
These source-body connection and body potential extraction regions will both be referred to below as charge collection regions. By suppressing floating body effects and preventing fluctuations in the body potential, they can increase the drain-source breakdown voltage of the device.
The current driving capability of an FET generally increases with the ratio (W/L) of the gate width (W) to the gate length (L). In the device structures disclosed by Hara and Hirano, the charge collection regions lie adjacent the source regions in the gate width direction. The more of this width that is devoted to the charge collection regions in order to increase the drain-source breakdown voltage, the smaller the width of the source regions becomes, decreasing the current driving capability. If the source regions are widened to provide more current driving capability the width of the entire device increases, making an adequate drain-source breakdown voltage incompatible with small device size.